1. Field of the Invention
The invention relates in general to a method for layout generation for an integrated circuits (IC), and more particular to a method for layout generation for a parameterized cell of an integrated circuit (IC) guided by design rule checking (DRC).
2. Description of the Prior Art
Analog circuit designers typically use parameterized cells (PCells) as building blocks to design analog ICs. PCells are design units which use parameter values to calculate IC layouts. An example is a PMOS PCell that takes channel width and channel length as parameters. After a user selecting the PMOS PCell and specifying values for the two parameters, a PMOS layout with the specified channel length and width is automatically generated and placed at the location indicated by the user. In addition, the generated layout satisfies all design rules that are typically described in a technology file which is set along with the definition of PCells initially. Thus, the generated PCell layout is free of design rule violations, which is also called “DRC clean”.
As process technology advances, new design rules become so complex that it's very difficult, if not impossible, to generate optimal layouts for PCells that are also DRC clean. The reason is that for many complex design rules, the PCell generator has to estimate the positions and dimensions of some geometry shapes that are yet to be generated. Often times, there is a deviation between the estimate and the actual numbers. So, to play safe, PCell generators typically take a conservative approach, namely, using larger dimensions and spacing that can satisfy worst case scenarios. With this approach, the generated layouts are typically less than ideal.
FIG. 1 is an example for prior art. It shows a MOS layout which a PCell generator may generate. The layout consists of polygon 100 on poly layer for the gate of the MOS transistor, polygon 102 on diffusion layer for the source and drain, polygons 104 and 114 on metal layer (metal 1) for source and drain connections, and polygons 106, 108, 110 and 112 on contact cut layer (metal 1 to poly cut layer) for metal to diffusion connections. Dimensions and locations of the polygons in FIG. 1 may be determined in one of the following ways:
1. They may be specified directly by the user. For example, the horizontal span of polygon 100 is the value of the channel length parameter specified by the user.
2. They may be determined by user specified values and design rule values specified in the associated technology file. For example, the vertical span of polygon 100 is the sum of channel width parameter value specified by the user plus twice of the minimum value of extension of poly over diff, which is specified in the technology file.
3. They may be determined by specifications in the technology file. For example, enclosures 120 and 122 are metal over contact minimum required values, and are specified in the technology file.
As process technologies advance, design rules become more and more complex. Design rule values, such as metal over contact enclosures, are no longer simple constant values. Let's take enclosure 120 and enclosure 122 in FIG. 1 as an example. For advanced design rules, enclosures 120 and 122 may depend on the dimensions of polygon 104, dimensions of polygon 114, the distance between 104 and 114, and the parallel run length between 104 and 114. In other words, in order to calculate the optimal values for 120 and 122, we need to know the dimensions of 104, 114, the distance in between, and the parallel run length between 104 and 114.
Typically, PCell layouts are generated in a sequential manner. In FIG. 1 for example, polygons 100, 102 and 104 may be generated first; then polygons 106 and 108 are generated. The values for metal to contact enclosures will decide where and how many the contact polygons (e.g. polygons 106, 108) are to be generated. For complex enclosure rules, the value is a function of the dimensions of metals 104 and 114, the distance in between, and the parallel run length between 104 and 114. However, at this moment, polygon 114 is not generated yet, and so its location and dimensions are not known. In order to calculate the values for 120 and 122, we have to estimate the dimensions and the location for polygon 114. Later, when polygon 114 is generated, if it comes out as exact as previously estimated, then everything is good. More often than not, the actual dimensions and location for 114 are different from original estimation, and a DRC violation may occur. To fix the DRC violation, we will need to go back to re-calculate the values for 120 and 122 with a better estimation for polygon 114, and re-generate portions of the layout. The new result may be all correct, or may be not. If it's not correct, the same steps will have to repeat once more. This makes the layout generation complicated.
Besides the example for enclosure issue shown above, there may be many other advanced design rules that have to be taken care of. Each design rule posts a different challenge and has to be satisfied in the final layout.
Therefore, what is needed is a systematic way to efficiently and effectively generate layouts that satisfy all the advanced design rules while not relying on the estimation of layout components that are yet to be generated.